Translator



Sept. 22, 1959 Filed April 4, 1956 sA-(as) 59 E. W. FLINT TRANSLATOR 2Sheets-Sheet 1 uffa) W. FL//VT By I ATTORNEY Sept. 22, 1959 E w F| |N' r2,905,934

TRANSLATOR Filed April 4,'1956 2 Sheets-Sheet 2 ii/35 vii/a6 uw vuesuur@ 3 l- TL- T: 'Tl 62 3 d 3 J J 45, 7a

By FL/NT A TTORNEV United States Patent O TRANSLATOR Erlon W. Flint,Mountain View, NJ., assigner to Bell Telephone Laboratories,Incorporated, New York, N.Y., a corporation of New York ApplicationApril 4, 1956, Serial No. 576,016

Claims. (Cl. 340-347) This invention relates to a ferromagnetictranslator and more specifically to a translator utilizing rectangularhysteresis loop cores as switching elements.

A translator is a `device which is employed to transfer informationcarried in one coding system to other coding systems encompassingdifferent numbering bases and signaling methods. Broadly, a translatoris a device, which, responsive to an inquiry in the form of electricallycoded numbers, supplies an answer in the form of an output code. In thecourse of the functioning of communication systems or devices, it may benecessary to perform one or more conversions or translations of theinput information. The susceptibility to erroneous translation of theinformation increases in direct proportion to the frequency with whichthe information is operated upon from a translation viewpoint.

In many communication devices including computing devices or `datatransmission systems, the necessity of accuracy in information handlingis paramount. For this reason it is essential that the translationprocess be governed in such a manner that erroneous translations aredetected and/or impeded.

It is therefore an object of this invention to provide an inherentlyself-checking arrangement in translating from one code base to another.

A further object of this invention is translation from athree-out-of-live code to a decimal system.

A feature of this invention is the use of only iive cores in translatingfrom a three-out-of-ve code to a decimal code.

Another feature of this invention is the use of electrical biaspotentials generated within the cores to impede rroneous translations.

These and other objects and features may be accomplished by a circuitincluding tive rectangular hysteresis loop cores as switching elements.The live cores are each wound with four individual translation windings,an input winding, an input bias winding, two output bias windings and anadvance winding. The translator is adapted to accept a digit in thethree-out-of-iive code, translate it to the two-out-of-iive code, andfinally convert to a one-in-ten code.

Translation is elected by the application of current to the input biaswindings in a direction adapted to change the magnetic state of all ofthe iive cores. Simultaneously, and for an equal duration or longer,currents are applied to three of the input windings corresponding to thethree-out-of-five code for the digit to be translated. These inputwinding currents are in a direction to prevent a change of magneticstate in the cores to which they are applied. Consequently, three of themagnetic cores are not changed in state, or set, but the remaining twoare. The windings of the cores and the configuration of the circuit arearranged to permit the two energized cores to represent the same decimaldigit as the three-out-of-iive input code, e.g., 0, l and 2 are thethree-outofve code representation for a decimal digit 2,905,934 PatentedSept. 22, 1959 f. ICC

O, while 4 and 7 are the corresponding two-out-of-ve code designations.

Subsequently, current is applied to the advance winding to restore tothe original state, or reset, those cores which were previously set. Inso doing, voltages will be induced which will produce an outputindication from one of the decimal translation windings if two, and onlytwo, cores were previously set. lf more than two or less than two coreswere previously changed in state, no output indication is made. In thelatter two instances, voltages induced in the output bias windings serveto oppose those of the decimal translation windings and prevent anyoutput therefrom.

The set and reset states, as explained above, are both stableconditions, and the cores herein employed remain for an indefiniteperiod in the state to which they are driven.

The above objects and features of the invention will be more readilyunderstood by reference to the accompanying description, appended claimsand drawings in which:

Fig. l is a diagram illustrating the relationship of current and fluxflow in a circuit employing magnetic core mirror symbols such as areused in Fig. 2;

Fig. 2 shows a circuit embodying the invention in conjunction with athree-out-of-five to decimal translator in which five magnetic cores,each incorporating nine separate windings, are employed;

Fig. 3 is the electrical equivalent of the circuit of Fig. 2 when twoinput conductors or elements are energized, constituting the normalcondition;

Fig. 4 is the electrical equivalent circuit of Fig. 2 when one inputelement or conductor is energized; and

Fig. 5 shows the electrical equivalent of the circuit of Fig. 2 whenthree input conductors or elements are energized.

It will be noted that in Figs. 3, 4 and S the smaller, heavier line inthe battery symbol is taken to represent the positive terminal of thebattery.

Referring now to Fig. l, a diagram is shown indicating the polarities ofapplied and induced currents in the windings of a coil determinable fromthe mirror symbols utilized in Fig. 2. The mirror symbol method ofrepresentation offers a convenient means of determining the polarity ofinduced voltages, or the direction of current flow in secondary windingson a core. Cores and conductors are represented by line segmentscrossing at right angles. A winding is represented by a mirror passingthrough the intersection at an angle of 45 degrees. Winding polarity isindicated by the slope of the mirror. The convention has been adoptedthat the current approaching the core is reliected off the mirror togenerate a resulting uX. If reiiected in an upward direction, it isconsidered to aid setting of the core, if downward, the flux tends toreset the core.

In Fig. l, it may be seen that the direction of the induced ux rp is inthe upward direction since the input current i1 is reected by the mirrorin an upwardly direction. The induced flux is traced to the end of thecore and retiected back as shown for (pr. Tracing the reected linx qa,back down the core and reflecting off each mirror, the direction ofcurrent iiow in the windings is established. It may be seen that theinduced current il. flows in the input winding 3 in a direction oppositeto the input current i1. This clearly conforms with Lenzs law. Thecurrent i2 in the secondary winding is in the direction shown since thereturn flux pr is reflected off the output winding 4, to the right.

For a further exposition of this type of notation, reference may be madeto an article entitled Pulse Switching Circuits Using Magnetic Cores, byM. Karnaugh, Proceedings of the LRE., vol. 43, number 5, p. 572, May

3 19545, and A Proposed Symbol for Magnetic Circuits, by R. P. Mayer,Engineering Note E-472, Digital Computer Laboratory, Mass. Inst. ofTech., August 14, 1952.

In Fig. 2f1ve cores 0, 1, 2, 4 and 7 are represented by vertical lines;Ten pairs of decimal translation wind# ings 10-19, 19,' are selectivelyyWound on the cores. Sinilarly,4 output bias windings 20;*,29 and inputbias wingin'gs 310--134` 'are wound through the cores. Separate inputwindings 35S-39 are wound on each ofthe tive cores, and finally, seriesconnected advance windings 40%4'4 are wound on the cores.

The number appearing in contiguity to the mirror slant notation in Ythelower right-hand corner thereof represents thev nuniber of turns on theassociated winding. It will be noted that, by way of example, variouswindings have been allocated differing numbers of turns which have beenfound suitable for the satisfactory operation of the particularembodiment illustrated.

plurality of unilateral conducting elements or diodes '45;60 are locatedon the output of each of the decimal translation windings and the outputbias windings. All of the' 'output bias windings 25-29 are paralleled toa eo'niinon bias Vresistance 61. The decimal translation windings 10,10'-19', 19" are individually associated with respective biasresistances 62-71. All of the decimal translation andl bias windingsVare ultimately c'ommoned into a single bias resistance 73.

`An electroresponsive device R is in parallel with each of ther'esistances 62-*771 associated with the decimal translation windings"10, IOL-19, 19. The devices are "shown in symbolic form in Figs. 2, 3',4 and S and it is understood that any electroresponsive device includinggalvanometers, marginal relays or other indicating devic'e'scapable ofdiscriminating between a very light now of current and a substantialcurrent and rendering an indcation' in the latter condition only, may beused.

In this respectvit may be observed that in lieu of the resistance's62-'71 associated with the decimal translation windings 19-#192 a groupof rectangular hysteresis loop `'cores similar to those utilized forcores 0, 1, 2, 4 and 7 may be employed. These cores have the inherentproperty of acting as switching device'swhich are transposedin state orset only by a substantial current flow and do not change state whensubjected to a veryl light current now. l p Having described thestructure constituting this ernbodiinent of Vthe invention, theoperation is as follows:

Assuming that the cores areoriginally in the reset state, translation isaccomplishedV by applying pulses to three of the input windings 35-39and to the series connected input bias windings`30=34 at the same time;

Assuming, for example, that the input windings 375,

36 and 37 of cores 0, 1 and 2 are energized by momentarily closingswitches 50, 51 and 52 and the' input bias windings 30-34 aresimultaneously energized by closing s witchSB, cores 4 and '7 will beset. This result follows since the uX occasioned by the flow of current(from left to right) in the input bias windings 3041-34 is reflected inan upward direction tending to set all the cores. This uX is opposed bydownward uxes produced in cores Q, 1 and 2 by current flow through inputwindings 35, 36 37. In consequence, the upward uXe's, due to the inputbiaswindings 33 and 34 on cores 4 and 7, set diese cores.

Subsequently, switch SA is closed momentarily, applying' a current pulseto windings 40'-44. This current 1s efleeted in a direction to producedownward fluxes tending to reset all the cores. Those cores which werepevlou'sly set, i.e., cores4 and 7, are now reset, undergoingsubstantial internal flux changes. If the fluxes on cores 4' and 7 'aretracedfto the end of the cores and then back up as explained in Fig; 1,it will be seen that certain useful voltages are induced in the windingson these cores'.

In core* 4, for example, theu'pward return ux is're- 4 flected byadvance Winding 43 to the left, indicating opposition to the ow ofcurrent in said winding in accordance with Lenzs law. Of the remainingwindings on core 4, windings 33, 2S, 23, 16', 15', 14 and 10 reect tothe right, winding 38 reecting to the left.

Current will not now through winding 33, although voltages are inducedtherein since switch SB was only momentarily closed and is now in theopen position. By the same token no current will flow in winding 38,although voltage is induced therein4 since switch 54 was onlymomentarily closed. The diodes associated with windings 28, 23, 16', 15'and 14 arepoled in a direction to permit the induced currentto flow, butas will be pointed out with reference to Fig. 3, these currents will besubstantially blocked by an opposing voltage on the cathode side oftheir associated respective diodes 59, 55, 51, 50 and 49. It may be seenthat current will now in winding 10 as will be verified in thediscussion of Fig. 3. Y l

If a similar analysis is made of ythe other 'core' ieset i.e., core 7,it willV be observed ,that winding 10' which is connected lin serieswithl winding 1010i obren, Vwill likewise conduct cur'rfent, saidcurrent flowing'k the associated diode 45, resistance 62 andresistancew73', to return over an obvious path;V As a result, electrofresponsive device R associated with resistance'y 62 is actuated by thepotential drop therecross. n

Thus itha's'wbeen seen that for the assumedvinpnt on windings 35, 36 and37 representing O, l, 2 in th'ejthree out-'of-iive code, a translationhas been eiectd t the representation 4 and V7 in the two-outpf-ve codeby the setting of cores 4 and 7, and subsequently lto the decimal valuezero in the base l0 code through the en= ergization of electroresponsiveindicatingv device R connected across resistance 62. n

Similarly, the devices R connected across resistances 63-71 representthe decimal values 1- 9, respectively.

Various other input combinations on the input windings will result intranslation t'o .other decimal representations as shown in the followingtable:

Input, three- Twdout- Ontpnt out-of-ve of-nve decimal o, 1, 2 4, 7 o` 2,4, 7 o, 1 1 1, 4, 7 V 0, 2 2 o, 4, 7 1, 2 3 l, 2, 7 0, 4 4 0, 2, 7 1, 45 U, l, 7 2, 4 6 1, 2, 4 0,7 7 0, 2, 4 1, 7 8 0, 1, 4 2, 7 9

In the previous illustration, translation from the threeout-of-nve codeto the one-in-ten ende wherein the correct number of elements, nainelythree, have been energized, has been described. Fig. 3jis the electricalequivalent of the circuit of Fig. 2 when three elements are energized toconstitute the normal condition'. Y In Fig. 3, the.

voltage induced in the windings oi Fig. 2 is indicated batteries whichare labeled in multiples ,of E, where E is the voltage induced in awinding in Fig. 2'of twelve turns.y Thus it rinay be seen` that theresetting of co'r'es 4 and 7 in Fig. 2 occasions the induced voltages inFig. 3 as sh'o'wn. Windings' 10 and '10', for eXample, each halvingtwelve turns contribute a total of 2E in series with diode 45, andresistance 62. Winding 14',- having twelve turns thereon, produces` avoltage of E through diode 49 and impedance 66. Similarly, windings15',- 16, 17',- 18 and 19 each produces a voltage of E through theirrespective diodes and resistances or indicatingA devices. Output biaswindings 23 and 24, each having 18 turns, contribute avoltage of 3E inAseries with diode SSand resistanceV 72. The two remaining energizedwindings 2s 'and 29 eh ctnbuts voltage of tl/zE iparue'i with'associated Vresistance 61. Y

Assuming for the purposes of the embodiment of Fig. 2 that resistances61--72 are each 6.81 ohms and that resistance 73 is 4.64 ohms, analysisof the equivalent circuit of Fig. 3 indicates that the decimaltranslation windings 14', 15', 16', 17', 18 and 19' have no currentowing therethrough since their associated diodes 49-54 will be cut oi bya voltage higher than E applied to their anode sides. In this case, biaswindings 23, 24, 28 and 29 produce sutcient current through theirassociated resistances 72 and 61 to back bias diodes 49-54 Diode 45,however, will be in the conducting condition since a voltage of 2E isapplied to the anode electrode of diode 45 and a lesser voltage isapplied to the cathode. As a result, current will ow through resistance62 and the associated electroresponsive device R to indicate a decimaltranslation of from the three-out-of-iive input code 0, 1, 2.

Fig. 4 is the electrical equivalent of the circuit of Fig. 2 when fourinput windings have been energized, resulting in the setting of only onecore, an invalid input combination. Assuming that core 7 is the onlycore to set, reference to Figs. 2 and 4 indicate that the followingconditions obtain:

A voltage of E is induced in windings 10', 17', 18', and 19'. Voltagesof 11/2E are induced in windings 24 and 29 as a result of theeighteen-turn windings thereon. Hypothesizing that the resistances inFig. 4 are equal to those already cited for Fig. 2, an analysis of thecircuit will indicate that a current iiows in resistance 73 which willbe suicient to produce a drop of substantially .9E volt thereacross.This will reduce the current through any of the decimal translationwindings 10', 17', 18 and 19' to a value insutiicient to actuate theirassociated electroresponsive apparatus R. It will be further apparent tothose skilled in the art that it is possible to cut oft the ow from thedecimal translation windings a1- together.

In this illustration it has been assumed that core 7, and core 7 only,has been set, but it will be observed that if any other core had beenset the equivalent circuit of Fig. 4 would nevertheless obtain,Similarly, although cores 4 and 7 have been assumed to be those coresthat had been set in the discussion of Fig. 3, it will be noted that anidentical electrical equivalent circuit would have been obtained had anyother two pairs of cores been set.

In the event that more than two cores had set, indicating a lessernumber of energized elements than the correct number; for example, ifcores 2, 4 and 7 had been set as a result of the energization of inputwindings 35 and 36, the electrical circuit conditions of Fig, wouldobtain.

Examining Figs. 2 and 5 it is seen that `a voltage of 2E in series isproduced by windings and 10', 16 and 16' and 19 and 19', and a voltageof E is induced in windings 12', 13', 14', 15' 17 and 18'. A voltage oflll/zE in series is produced by the bias windings 22, 23 and 24, andfinally Ia voltage of 11/2E is each produced by windings 27, 28 and 29.

Analysis of the circuit, assuming the same circuit parameters aspreviously given, indicates that the path through resistance 72 anddiode 55 which has 412E in series therewith predominates over all otherinduced voltages, causing a current iiow through resistance 73suliicient to cut off all other paths.

Thus it has been shown that the decimal translation windings 10, 10'-19,19' will have a current ilow therethrough of a substantial degree,suicient to operate the indicating devices R associated therewith onlyin the event that two cores have been set, indicating an input code ofthree-outofiive. If more than three or less than three input windingsare activated, indicating an incorrect number of input elements, nooutput is producedl inasmuch as no associated indicating device R isactivated. Thus far situations have been examined in which one core, twocores and three cores have been set. If more than three cores, forexample, four or iive cores, are set, the circuit is similar to that ofFig. 5, with the exception that the blocking action produced by the biaswindings 20-24 is even more positive, producing bias voltages of 6E and71/2E, respectively, which are more than suficient to cut oli all of theother diodes in the circuit.

In this respect it may be observed that the arbitrary induced voltage Eproduced at the time that the cores are reset need not necessarily bethe same when different numbers of cores are set and reset. Neverthelessthe ratios of the voltages induced in the various windings of aparticular core remain the same since the turns ratio bears a fixedrelationship in the circuit.

It may be seen that the embodiment depicted in Fig. 2 may be used as` atwo-out-of-iive to one-in-ten code translator by the application of theinput signals to the selected two of the input windings 35-39 in adirection opposite to that shown to set the assocated cores. Under theseconditions two of the switches 74-78 are shifted to negative battery andno signal is applied to the input bias windings. The remainingvoperation is identical with that described above.

It is understood that the embodiments shown are merely exemplary andthat various modifications will be apparent to those skilled in the artwithout departing from the scope of the present invention.

What is claimed is:

1. A ferromagnetic translator comprising a plurality of rectangularhysteresis loop cores, a plurality of translation windings and outputbias windings on each of said cores, said translation windings andoutput bias windings being wound according to a code, an input windingon each of said cores adapted to receive a signal characterizing theinformation to be translated, an input bias winding on each of saidcores adapted when energized to change the magnetic state of `any coreon which the input winding is not simultaneously energized, an advancewinding on each of said cores adapted when energized to restore any corein which the magnetic state has been changed to its original magneticstate, a plurality of diodes connected to said translation windings andsaid output bias windings, means for simultaneously energizing saidinput bias windings and a predetermined number of said input windings toset a predetermined number of cores, and means for thereafter energizingsaid advance winding to reset said cores thereby inducing currents inthe translation windings thereon, said diodes being operative inresponse to opposing potentials induced in said output bias windings toimpede the flow of current in said translation windings when the numberof cores set is other than the predetermined number.

2. A ferromagnetic translator comprising a plurality of rectangularhysteresis loop cores, a plurality of translation and output biaswindings on each of said cores, said translation windings being wound toexpress the value of a digit according to a code, an input winding oneach of said cores adapted to receive a signal characterizing theinformation to be translated, an input bias winding on each of saidcores adapted when energized to change the magnetic state of any core onwhich the input winding is not simultaneously energized, an advancewinding on each of said cores adapted when energized to restore any corein which the magnetic state has been changed to its original magneticstate; a plurality of diodes connected to said translation windings andsaid output bias windings, means for simultaneously energizing saidinput bias windings and a predetermined number of said input windings toset a predetermined number of cores, and means for thereafter energizingsaid advance winding to reset said predetermined number of coresinducing current in the translation windings thereon, said diodes beingoperative, in response to opposing potentials induced in said outputbias windings when the number of cores energized is other than thepredetermined number, to impede the flow of induced currents -in saidtranslation windings.V

- 3; A ferromagnetic three-outL-of-iive to decimal trans'- lator'comprising a plurality 'of Vrectangular hysteresis loop cores, aplurality of decimal translation windings on each of s'aid cores, saidtranslation windings being wound according to a `code,.an input winding'and an input bias winding on each of said cores, meansrforsimultaneously energizing all of said input bias windings land. apredetermined number` of said input windings thereby setting any core inwhich the input winding is not energized, an advance winding o'n each ofsaid cores adapted when energized to reset all of said cores, outputbias windings on each of said cores, a plurality of diodes connected toone end of said decimal translation windings and said outputbiaswindings, a common impedance joining said diodes to the other 'endof said decimal translation windings and output bias windings to form aclosed electrical circuit, and means for detecting signals in saiddecimal translation windings t'o identify the decimal translation of aparticular input code applied to said input windings, said means beingoperable in response to opposing potentials induced in said output bias`windings lto impede the dow of induced currents in said translationwindings when the number of input windings energized `is other than thepredetermined number.

4. A ferromagnetic three-out-of-ve to vdecimal translator comprising aplurality of hysteresis 'loop cores, four decimal translation windingswound on each of said cores according to la code, a plurality of outputbias windings on each of said cores adapted when energized to oppose thepotentials linduced in said decimal translation windings,ian`inputwinding and an input bias winding on each of said cores, means forsimultaneously energizing all of said input bias windings and three ofsaid input windings thereby Setting the two cores in which the inputwindings remain unenergized, an advance winding on each ofsaid coresadapted when energized to restore the magnetic state of any core thathas previously been set thereby inducing currents in the decimaltranslation windings thereon, means `for detecting induced currents insaid translation windings thereby effecting translation to 'a decimalcode, a plurality of diodes connected to Vone end of said decimaltranslation windings and said output biaswindings, a plurality ofimpedances connected in series with said diodes, means interconnectingsaid plurality of impedances, Vand a common impedance joining saidplurality of impedances to the other end of Vsaid decimal translationand output bias windingsto form a closed electrical path, diodes beingoperative in response to opposing potentials induced in said output biaswindings to impede the ow of current in said decimal tra'nslationwindings when the number of cores set is other than two. n

5. YA ferromagnetic three-out-of-fiveto decimal translatorrcomprisingtive rectangular hysteresis `loop cores, four decimal translationwindings wound on each of said cores according to a code, two outputbias windings on each of said cores adapted when energized to oppose thepotentials induced in said decimal ltranslation windings, an inputwinding and an input bias winding on each of said cores, means forsimultaneously energizing all of said input bias windings and three ofsaid input windings thereby setting the two cores lin. which the inputwindings remain unenergized, an advance winding on 'each of said coresadapted when energized to Vrestore theV previous magnetfic state vof anycore that has previously been set, a plurality of diodes connected toone end of said decimal translation windings and said output biaswindings, a plurality of impedan'ces connected in series with saiddiodes, means interconnecting said plurality of impedancjes, Va commonimpedance joining said plurality of imp edances' to the other end ofsaid decimal translation windings vand output ybias windings to -form aclosed electrical path,-and current-detecting means connected Atosaiddec'rmal translation windings to identify the decirnalrtran'slationof aparticul'ar input EVcode applied to said input windings, saidvdiodes, being operable in response tolopposin'g potentials induced insaid output bias windings toimpede the how `of -current in said 'decimaltranslation windings thereby to prevent an Aerroneous translation whenthe number of cores energizedis other than two. A

6. A ferromagnetic translator vcomprising apluralit'y 'of rectangularhysteresis loop cores, `a plurality of translation and output biaswindings one'ach Tof said cores, said translation windings and outputbias windings being wound a'c; cording to a code, an input winding oneach of said cores adapted when energized to change the magnetic stateof the core on which said input winding is wound, an fad- Vance winding'on each of said core adapted when energized to restore any 'core inwhich the magnetic state has been changed from its original magneticstate, a plurality of diodes connected to "s'aid translation windingsand said output bias windings, means for energizing "a predeterminednumber of said input windings according 'to a code thereby to change themagnetic state of a predetermined number of cores, and means forthereafter energizing said advance winding to restore said predeterminednumber of cores thereby inducing currents iin the Vtranslation windingsthereon, said diodes beingV operative, in response to opposingpotentials induced in said output bias windings when thenumbe'r of'cores energized isother than the predetermined number, 'to impede vtheflow of induced cur# rents in said translation windings. Y Y 7. Aferromagnetic 'translator comprising a 'plurality of rectangularhysteresis loop cores, a plurality Iof, ltranslation windings and outputbias windings on'each of said cores, saidftranslatio'n windings :andloutput bias windings being wonnd according to 4a code, -an inputwinding on each of said cores ladapted when energized to set the core onwhich 'said winding is situated, an advance windingon each of said coresadapted when energized to res'et any core which was Vpreviously set, laplurality of diodes connected to said translation windings and saidoutput Ibias windings, a plurality of impedances connected 'to saiddiodes, `ir'ieans for energizing a predetermined number of said inputwindings to set a predetermined numbero'f cores, and means Vforthereafter energizing said advance winding to reset said cores therebyinducing currents in the translation windings thereon.

8. A ferromagnetic two-out-of-iive to decimal translator comprising aplurality-of rectangular hysteresis loop cores, a plurality xof decimaltranslation windings oneach of said cores woundV accordmg to a code, aninput winding on each lof said cores adapted when energized to set thecore on which it islocated, an advance winding on each of said coresadapted when energized `to restore any core in which the magnetic stratehas been changed 'from its original magnetic state, a plurality Vofoutput bias windings on each o'f said cores, a plurality ofV diodesconnected to one end of said decimal translation windings and saidoutput bias windings, a plurality of impedances connected to saiddiodes, means interconnecting said plurality of impedances, a commonimpedance joining saidplurality of impedances to the other end of saidtranslation decimal windings and output bias windings to forml a closedelectrical circuit, means for energizing a predetermined num# ber ofsaid input windings, means for thereafter energizing said advancewinding tol induce currents in said decimal translation windings, andmeans for detecting signals -in said decimal translation windings toidentify the decimal translation of a particular input code applied tosaid input windings, saidrdiodes being operative in response to opposingpotentials induced in said output bias windings to impede the flow ofinduced currents in said translation windings when the number of coresenergized is greater than the predetermined number. A

9. A ferromagnetic two-out-of-.veV to decimal translator comprising aplurality of hysteresis loop cores, lfoufr decimal translation windingswound on each of 'said cores according to a code, a plurality of outputbias windings n each of said cores adapted when energized to oppose thepotentials induced in said decimal translation windings, an inputwinding on each of said cores adapted when energized to set the magneticcore on which it is located, an advance winding on each of said coresadapted when energized to reset said core, means for energizing two ofsaid input windings, means for thereafter energizing said advancewinding thereby inducing currents in a number of decimal translationwindings, a plurality of diodes connected to one end of said decimaltranslation windings and said output bias windings, a plurality ofimpedances connected in series with said diodes, and a common impedancejoining said plurality of impedances to the other end of said decimaltranslation and output bias windings to form a closed electrical path,said diodes being operative in response to opposing potentials inducedin said output bias windings to impede the ow of current in said decimaltranslation windings when the number of cores set is other than two.

10. A ferromagnetic two-out-of-fve to decimal translator comprising fiverectangular hysteresis loop cores, four decimal translation windingswound on each of said cores according to a code, two output biaswindings on each of said cores adapted when energized to oppose thepotentials induced in said decimal translation windings, an inputwinding on each of said cores adapted when energized to change the stateof the core on which said winding is situated, an advance winding oneach of said 10 cores adapted when energized to reset any core that has'previously been set, means for energizing two of said input windings,means for thereafter energizing said advance winding thereby inducingcurrents in said decimal translation windings, a plurality of diodesconnected to one end of said decimal translation windings and saidoutput bias windings, a plurality of impedances connected in series withsaid diodes, means interconnecting said plurality of impedances, acommon impedance joining said plurality of impedances to the other endof said decimal translation windings and output bias windings to form aclosed electrical path, and current detecting means connected to saiddecimal translation windings to identify the decimal translation of aparticular input code applied to said input windings, said diodes beingoperable in response to opposing potentials induced in said output biaswindings to impede the tlow of current in said decimal translationwindings to prevent an erroneous translation when the number of coresenergized is other than two.

References Cited in the le of this patent UNITED STATES PATENTS2,637,017 Holden Apr. 28, 1953 2,695,397 Anderson Nov. 23, 19542,734,182 Rajchman Feb. 7, 1956 2,768,367 Rajchman Oct. 23, 19562,817,079 Young Dec. 17, 1957

